Power semiconductor die are well known which have spaced electrodes on a bottom surface, which are to be mounted, as by soldering to conforming metal patterns on a support board such as an FR-4 printed circuit board, or the like. As package size reduces, the electrodes also reduce in area and spacing, thus aggravating electro migration problems in solder contacts; the thermal performance of the device and difficulty of placing the package on the support board with exacting positional tolerance.
FIG. 1, shows a chip-scale semiconductor package 10 according to the prior art which includes a conductive clip (or can) 12 formed from a conductive material such as copper, and a semiconductor device 14, such as a power MOSFET. The package 10 is sold by the International Rectifier Corporation under the trade mark Direct FET®.
Semiconductor device 14 includes a first electrode 16, which is connected by, for example, solder, conductive epoxy or the like to the interior surface of clip or can 12. Semiconductor device 14 further includes another electrode 18 on an opposing surface thereof which is adapted for electrical connection by solder, conductive epoxy or the like to a respective conductive pad on a circuit board. Semiconductor 14 may also include a control electrode 20 adjacent electrode 18 which is also adapted for electrical connection in a manner similar to electrode 18. Further detail regarding a semiconductor package according to prior art can be found in U.S. Pat. No. 6,624,522, which is assigned to the assignee of the present application.
Semiconductor device 14, may be a power MOSFET die and electrodes 16, 18 and 20 are its, drain, source and gate electrodes, respectively. The flange of can 12, which is at the potential of source electrode 16, and contacts 18 and 20 terminate in a common plane to facilitate their connection to the matching pads on a receiving board surface.
As the device size reduces, the areas and spacing of contacts 18, 20 and the flange of can 12 reduce, reducing thermal performance and increasing the danger of shorting the electrodes through solder-bridging growth of dendrites. Reduced pad areas are also more susceptible to electromigration. In this case, solder may migrate, creating voids in the solder joint and increased joule heating and the risk of open circuit failures.
A device such as the one shown by FIG. 1 is usually manufactured by first stamping or punching clip (or can) 12 out of a conductive material, and then placing semiconductor device 14 therein using, for example, a pick and place method.